Renesas Electronics /R7FA6T2BD /SCI_B0 /XCR0

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Interpret as XCR0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TCSS 0 (0)BFE 0 (0)CF0RE 0 (00)CF1DS 0 (0)PIBE 0 (000)PIBS0 (0)BFOIE 0 (0)BCDIE 0 (0)BFDIE 0 (0)COFIE 0 (0)AEDIE 0 (00)BCCS

BFOIE=0, BFDIE=0, PIBE=0, CF0RE=0, COFIE=0, CF1DS=00, BFE=0, BCCS=00, AEDIE=0, PIBS=000, BCDIE=0

Description

Simple LIN Control Register 0

Fields

TCSS

Timer count clock source selection

1 (01): TCLK/4

2 (10): TCLK/16

3 (11): TCLK/64

BFE

Break Field enable

0 (0): No Break Field

1 (1): With Break Field

CF0RE

Control Field 0 enable

0 (0): No Control Field 0

1 (1): With Control Field 0

CF1DS

Control Field1 compare data select

0 (00): Select XCR1.PCF1D[7:0] as the compare data

1 (01): Select XCR1.SCF1D[7:0] as the compare data

2 (10): Select both XCR1.PCF1D[7:0] and XCR1.SCF1D[7:0] as the compare data

3 (11): Setting prohibited

PIBE

Priority interrupt bit enable

0 (0): Priority interrupt bit disable

1 (1): Priority interrupt bit enable

PIBS

Priority interrupt bit select

0 (000): bit 0 of Control Field 1

1 (001): bit 1 of Control Field 1

2 (010): bit 2 of Control Field 1

3 (011): bit 3 of Control Field 1

4 (100): bit 4 of Control Field 1

5 (101): bit 5 of Control Field 1

6 (110): bit 6 of Control Field 1

7 (111): bit 7 of Control Field 1

BFOIE

Break Field output completion interrupt enable

0 (0): Break Field output completion is not included in SCIn_TXI interrupt factor

1 (1): Break Field output completion is included in SCIn_TXI interrupt factor

BCDIE

Bus conflict detection interrupt enable

0 (0): Bus conflict detection is not included in SCIn_ERI interrupt factor

1 (1): Bus conflict detection is included in SCIn_ERI interrupt factor

BFDIE

Break Field detection interrupt enable

0 (0): Break Field detection interrupt disable

1 (1): Break Field detection interrupt enable

COFIE

Counter overflow interrupt enable

0 (0): Counter overflow is not included in SCIn_ERI interrupt factor

1 (1): Counter overflow is included in SCIn_ERI interrupt factor

AEDIE

Active edge detection interrupt enable

0 (0): Active edge detection interrupt disable

1 (1): Active edge detection interrupt enable

BCCS

Bus conflict detection clock selection

0 (00): Base clock

1 (01): Base clock/2

2 (10): Base clock/4

3 (11): Setting prohibited

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